1. Field of the Invention
The present invention relates to a clock generation circuit for generating a synchronous clock from two-phase resolver signals, an analog-digital angle converter having the clock generation circuit, and an angle detection apparatus.
2. Description of the Related Art
FIG. 12 shows a clock generation circuit used in a conventional angle converter disclosed in Japanese Patent No. 3,100,211 (Japanese Patent Application Laid-Open No. H5-172505).
A resolver signal K1=K sin θ sin ωt and a resolver signal K2=K cos θ sin ωt obtained, for example, in a resolver 1A are input to an analog-digital converter (hereinafter called an A-D converter) 2. The resolver signals K1 and K2 are also input to a pair of squaring circuits 3a and 3b, respectively. The squaring circuits 3a and 3b square the resolver signals K1 and K2 to output squared signals Y1=K2 sin2 θ sin2 ωt and Y2=K2 cos2 θ sin2 ωt. An adding circuit 4 adds the squared signals Y1 and Y2 to output a sum signal 4a=K2 sin2 ωt because sin2 θ+cos2 θ=1. A square-root circuit 5 square-roots the sum signal 4a to output a signal R=K sin ωt. A level adjustment circuit 6 adjusts the amplitude of the signal R to output a signal K′ sin ωt. This signal K′sin ωt is input to a REF terminal 2c of the A-D converter 2. The A-D converter 2 uses the signal K′ sin ωt as a synchronous clock and outputs a digital angle signal 2d from the angle signals K1 and K2.
As described above, the conventional clock generation circuit requires the square-root circuit in order to obtain the synchronous clock. Since the square-root circuit uses an analog multiplier, it is relatively expensive.